TDA5240 Datasheet, PDF (261/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
IMMIDFC
2
IMFSYNCC 1
IMWUC
0
Type
w
w
w
Description
Mask Interrupt on "Message ID Found" for Configuration C
0_B Interrupt enabled
1_B Interrupt disabled
Reset: 0_H
Mask Interrupt on "Frame Sync" for Configuration C
0_B Interrupt enabled
1_B Interrupt disabled
Reset: 0_H
Mask Interrupt on "Wake-up" for Configuration C
0_B Interrupt enabled
1_B Interrupt disabled
Reset: 0_H
Self Polling Mode Active Periods Register
SPMAP
Self Polling Mode Active Periods Register
Offset
096_H



8186('

630$3
Z
Field
Bits
UNUSED
7:5
SPMAP
4:0
Type
-
w
Description
UNUSED
Reset: 0_H
Self Polling Mode Active Periods value
Min: 01h = 1 (Master) Period
Max: 1Fh = 31(Master) Periods
Reg. value 00h = 32 (Master) Periods
Reset: 01_H
Self Polling Mode Idle Periods Register
Reset Value
01_H

SPMIP
Self Polling Mode Idle Periods Register

Data Sheet
Offset
097_H
630,3
Z
261
Reset Value
01_H

V4.0, 2010-02-19