TDA5240 Datasheet, PDF (123/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
2.7
Definitions
Functional Description
2.7.1 Definition of Bit Rate
The definition for the bit rate in the following description is:
bitrate = ^{s---y----m---s--b---o---l--s-}
If a symbol contains n chips (for Manchester n=2; for NRZ n=1) the chip rate is n times
the bit rate:
chiprate = n × bitrate
2.7.2 Definition of Manchester Duty Cycle
Several different definitions for the Manchester duty cycle (MDC) are in place. To avoid
wrong interpretation some of the definitions are given below.
Level-based Definition
MDC = Duration of H-level / Symbol period
bit = 1
1
0
0
1
1. chip
2. chip
T_{c hip}
T
b it
MDC < 50%
1
1
0
0
1
ΔT
T
c hip
T
H
T
b it
MDC > 50%
T
H
T
b it
ΔT
T
c hip
T_H
T_{b it}
T_H
T_{b it}
Figure 88 Definition A: Level-based definition
This definition determinates the duty cycle to be the ratio of the high pulse width and the
ideal symbol period. The DC content is constant and directly proportional to the specified
duty cycle.
For ΔT > 0 the high period is longer than the chip-period and for ΔT < 0 the high period
is shorter than the chip-period.
Data Sheet
123
V4.0, 2010-02-19