TDA5240 Datasheet, PDF (78/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
In default mode the Strobe signal is active high and has a delay of T_BIT/16 relative to the
data bit and a duration of T_BIT/2. The polarity of the Strobe signal is programmable, this
can be done via PPCFG2 register.
RXD
D_n
D_n+1
RXSTR
TBIT/16
TBIT/2
Figure 48 Timing of the Packet Oriented Transparent Payload Mode
Transparent Mode - Chip Data and Strobe (TMCDS)
The receiver’s simple plain data interface in this Transparent Mode is shown in
Figure 49. In this mode, the demodulated data signal is made directly available on the
data output pin of the data interface. Concurrently, an estimate of the chip clock is
optionally provided on the respective clock output line. Note that a sensible chip clock
can only be generated if the selected line encoding exhibits a constant chip rate. The
chip clock generation can be significantly improved by using a run-in signal of alternating
one-zero chips (maximum number of transitions within a data stream).
bit
synchronizer
TDA5240
data
interface
RX data
RX chip strobe
scheduler
Figure 49 Data interface for the Transparent Mode - Chip Data and Strobe
In the TDA5240, there is a specific digital output line for the chip clock estimate as well
as for the data output line, which delivers the encoded chip data. During inactivity of the
receiver, the line is in default mode switched to low.
The PPx pin provides the estimated chip clock, if CH_STR is selected. Further details
are given in Chapter 2.5.3.
Data Sheet
78
V4.0, 2010-02-19