TDA5240 Datasheet, PDF (83/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
FIFO Lock Behavior
The FIFO possesses a lock mechanism that is enabled via the SFR control bit FIFOLK
in the CMC1 register. If this mechanism is enabled, the FIFO will enter a FIFO Lock state
at the detection of the EOM criterion. During the time that the FIFO is locked, it is not
possible to receive additional data in Run Mode Self Polling. This means that it is only
possible to detect another wake-up in the Self Polling Mode, but no more data in the Run
Mode Self Polling. This will guarantee that only the first complete data packet is stored
in the FIFO. Enabling FIFOLK also locks the digital receive chain at EOM until release
from FIFO lock state.
The FIFO will remain locked unless one of three conditions occurs:
1.) The remaining contents of the FIFO are completely read out via the SPI
2.) The SFR control bit FIFOLK is cleared
3.) INITFIFO at Cycle Start is set in the CMC1 register and
a) FSM is switched to Run Mode Slave or
b) FSM switches from Self Polling Mode to Run Mode Self Polling
INITFIFO (Init Fifo@ Cycle Start) = 1
Accept Data
Write Data into FIFO
EOM=0
EOM=1
EOM=1
FIFOLK=0 FIFOLK=1
FIFO Lock
Wait till FIFO is empty
FIFO Empty = 0
FIFOLK=1
FIFOLK=0 FIFO Empty=1
Figure 54 FIFO Lock Behavior
Data Sheet
83
V4.0, 2010-02-19