TDA5240 Datasheet, PDF (227/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
SDCNT1
1
SDCNT0
0
Type
w
w
Description
Signal Detector Threshold Counter for Wakeup
0_B Disabled
1_B 1/2 bit
Reset: 0_H
Signal Detector Threshold Counter for Run Mode
0_B Disabled
1_B 1/2 bit
Reset: 0_H
FSK Noise Detector Threshold Register
A_NDTHRES
FSK Noise Detector Threshold Register

Offset
044_H
1'7+5(6
Z
Field
Bits
NDTHRES 7:0
Type
w
Description
FSK Noise Detector Threshold
Reset: 00_H
FSK Noise Detector Configuration Register
Reset Value
00_H

A_NDCONFIG
FSK Noise Detector Configuration Register
Offset
045_H


1'56(/
Z


1'6(/
Z


1'7/
Z
Field
Bits
NDRSEL
7:6
Type
w
Description
FSK Noise Detector Range Selection
00_B 2^7
01_B 2^6
10_B 2^5
11_B 2^4
Reset: 0_H
Data Sheet
227
Reset Value
07_H


1'3'65
Z
V4.0, 2010-02-19