TDA5240 Datasheet, PDF (271/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
MCS
3:2
SLRXEN
1
MSEL
0
Type
w
w
w
Description
Multi Configuration Selection (Run Mode Slave / Self Polling Mode)
00_B Config A / Config A
01_B Config B / Config A + B
10_B Config C / Config A + B + C
11_B Config D / Config A + B + C + D
Reset: 0_H
Slave Receiver Enable
This Bit is only used in Operating Mode Run Mode Slave / Sleep Mode
0_B Receiver is in Sleep Mode
1_B Receiver is in Run Mode Slave
Reset: 0_H
Operating Mode Selection
0_B Run Mode Slave / Sleep Mode
1_B Self Polling Mode
Reset: 0_H
Wakeup Peak Detector Readout Register
RSSIPWU
Wakeup Peak Detector Readout Register

Offset
0A7_H
566,3:8
U
Reset Value
00_H

Field
Bits
RSSIPWU
7:0
Type
r
Interrupt Status Register 0
Description
Peak Detector Level at Wakeup
Set at every WU event and also set at the end of every
configuration/channel cycle within a Self Polling period.
Cleared at Reset only.
Reset: 00_H
IS0
Interrupt Status Register 0

(20%
UF
Data Sheet

0,')%
UF

)6<1&%
UF
Offset
0A8_H


:8%
UF
(20$
UF
271

0,')$
UF
Reset Value
FF_H


)6<1&$
UF
:8$
UF
V4.0, 2010-02-19