TDA5240 Datasheet, PDF (241/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
BANDSEL
7:6
PLLINTC1
5:0
Type
w
w
Description
Frequency Band Selection
00_B not used
01_B 915MHz/868MHz
10_B 434MHz
11_B 315MHz
Reset: 2_H
SDPLL Multi Modulus Divider Integer Offset value for Channel 1
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13_H
PLL Fractional Division Ratio Register 0 Channel 1
A_PLLFRAC0C1
PLL Fractional Division Ratio Register 0
Channel 1
Offset
05A_H

3//)5$&&
Z
Reset Value
F3_H

Field
Bits
PLLFRAC0C1 7:0
Type
w
Description
Synthesizer channel frequency value (21 bits, bits 7:0), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: F3_H
PLL Fractional Division Ratio Register 1 Channel 1
A_PLLFRAC1C1
PLL Fractional Division Ratio Register 1
Channel 1
Offset
05B_H

3//)5$&&
Z
Reset Value
07_H

Data Sheet
241
V4.0, 2010-02-19