TDA5240 Datasheet, PDF (220/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
CODE
5:4
CHIPDINV 3
DINVEXT
2
AAFBYP
1
AAFFCSEL 0
Type
w
w
w
w
w
Description
Encoding Mode Selection
00_B Manchester Code
01_B Differential Manchester Code
10_B Biphase Space
11_B Biphase Mark
Reset: 0_H
Baseband Chip Data Inversion for CH_DATA and Decoder/Framer
input. Therefore Inverted Manchester and Inverted Differential
Manchester can be decoded internally.
0_B Not inverted
1_B Inverted
Reset: 0_H
Data Inversion of signal DATA and DATA_MATCHFIL for External
Processing
0_B Not inverted
1_B Inverted
Reset: 0_H
Anti-Alliasing Filter Bypass for RSSI pin
0_B Not bypassed
1_B Bypassed
Reset: 0_H
Anti-Alliasing Filter Corner Frequency Select
0_B 40 kHz
1_B 80 kHz
Reset: 0_H
RSSI Peak Detector Bit Position Register
A_PKBITPOS
RSSI Peak Detector Bit Position Register

Offset
037_H
566,'/<
Z
Reset Value
00_H

Field
Bits
RSSIDLY
7:0
Type
w
Description
RSSI Detector Start-up Delay for RSSIPPL register
Min: 00h: 0 bit delay (Start with first bit after FSYNC)
Max: FFh: 255 bit delay
Note: Due to filtering and signal computation, the latency T1 and T2 have
to be added
Reset: 00_H
Data Sheet
220
V4.0, 2010-02-19