TDA5240 Datasheet, PDF (244/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

PLL Fractional Division Ratio Register 2 Channel 2
TDA5240
Appendix
Register Description
A_PLLFRAC2C2
PLL Fractional Division Ratio Register 2
Channel 2
Offset
060_H




8186('
3//)&20
3&

Z
3//)5$&&
Z
Reset Value
09_H

Field
Bits
UNUSED
7:6
PLLFCOMPC2 5
PLLFRAC2C2 4:0
Type
-
w
w
Description
UNUSED
Reset: 0_H
Fractional Spurii Compensation enable for Channel 2
0_B Disabled
1_B Enabled
Reset: 0_H
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 2
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09_H
PLL MMD Integer Value Register Channel 3
A_PLLINTC3
PLL MMD Integer Value Register Channel 3



8186('

Offset
061_H
3//,17&
Z
Reset Value
13_H

Field
Bits
UNUSED
7:6
PLLINTC3
5:0
Type
-
w
Description
UNUSED
Reset: 0_H
SDPLL Multi Modulus Divider Integer Offset value for Channel 3
PLLINT(5:0) = dec2hex(INT(f_LO / f_XTAL))
Reset: 13_H
PLL Fractional Division Ratio Register 0 Channel 3
Data Sheet
244
V4.0, 2010-02-19