TDA5240 Datasheet, PDF (242/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
PLLFRAC1C1 7:0
Type
w
Description
Synthesizer channel frequency value (21 bits, bits 15:8), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 07_H
PLL Fractional Division Ratio Register 2 Channel 1
A_PLLFRAC2C1
PLL Fractional Division Ratio Register 2
Channel 1
Offset
05C_H




8186('
3//)&20
3&

Z
3//)5$&&
Z
Reset Value
09_H

Field
Bits
UNUSED
7:6
PLLFCOMPC1 5
PLLFRAC2C1 4:0
Type
-
w
w
Description
UNUSED
Reset: 0_H
Fractional Spurii Compensation enable for Channel 1
0_B Disabled
1_B Enabled
Reset: 0_H
Synthesizer channel frequency value (21 bits, bits 20:16), fractional
division ratio for Channel 1
PLLFRAC(20:0) = dec2hex(((f_LO / f_XTAL) - PLLINT) * 2^21)
Reset: 09_H
PLL MMD Integer Value Register Channel 2
A_PLLINTC2
PLL MMD Integer Value Register Channel 2



8186('

Offset
05D_H
3//,17&
Z
Reset Value
13_H

Data Sheet
242
V4.0, 2010-02-19