TDA5240 Datasheet, PDF (236/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
TSIGAP
7:3
GAPVAL
2:0
Type
w
w
Description
TSI Gap (T/2 bit resolution)
1Fh: 15 1/2 bit gap
00h: 0 bit gap
TSIGAP is used to lock the PLL after TSI A is found, if the TSI detection
mode 10b is selected.
Reset: 00_H
TSI Gap (T/16 bit resolution)
111b: 7/16 bit gap
000b: 0 bit gap
GAPVAL is used to correct the DCO phase after TSIGAP time, if
A_TSIMODE.TSIGRSYN is disabled
Reset: 0_H
TSI Pattern Data Reference A Register 0
A_TSIPTA0
TSI Pattern Data Reference A Register 0

Offset
051_H
76,37$
Z
Reset Value
00_H

Field
Bits
TSIPTA0
7:0
Type
w
Description
Data Pattern for TSI comparison: Bit 7...Bit 0(LSB) (in Chips)
Reset: 00_H
TSI Pattern Data Reference A Register 1
A_TSIPTA1
TSI Pattern Data Reference A Register 1

Offset
052_H
76,37$
Z
Reset Value
00_H

Field
Bits
TSIPTA1
7:0
Data Sheet
Type
w
Description
Data Pattern for TSI comparison: Bit 15(MSB)...Bit 8 (in Chips)
Reset: 00_H
236
V4.0, 2010-02-19