TDA5240 Datasheet, PDF (252/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

Clock Divider Register 0
TDA5240
Appendix
Register Description
CLKOUT0
Clock Divider Register 0

Offset
086_H
&/.287
Z
Reset Value
0B_H

Field
Bits
CLKOUT0
7:0
Type
w
Clock Divider Register 1
Description
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 0B_H
CLKOUT1
Clock Divider Register 1

Offset
087_H
&/.287
Z
Reset Value
00_H

Field
Bits
CLKOUT1
7:0
Type
w
Clock Divider Register 2
Description
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 00_H
CLKOUT2
Clock Divider Register 2
Data Sheet
Offset
088_H
252
Reset Value
00_H
V4.0, 2010-02-19