TDA5240 Datasheet, PDF (233/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
Type
TVWIN
7:0
w
Slicer Configuration Register
Description
Timing Violation Window Length.
Defines the maximal number of 1/16 data samples without detected edge
which will be tolerated by CDR with no Loss of Symbol Synchronization
28h: 40/16 bit ((8 + 16 *CV + 8)*1.25)
FFh: 255/16 bit
Note: in TSIGAP mode the value must be higher.
Reset: 28_H
A_SLCCFG
Slicer Configuration Register

Offset
04C_H
6/&&)*
Z
Reset Value
90_H

Field
Bits
SLCCFG
7:0
Type
w
TSI Detection Mode Register
Description
Data Slicer Configuration
Value 90_H : Chip Mode EOM-CV: For patterns with code violations in data
packet and optimized for activated EOM code violation criterion (and
optional EOM data length criterion)
Value 94_H : Chip Mode EOM-Datalength: For patterns with code
violations in data packet and optimized for activated EOM data length
criterion only (EOMDATLEN)
Value 95_H : Chip Mode Transparent: When Framer is not used, but
CH_DATA / CH_STR are used for data processing
Value 75_H : Bit Mode: Only for patterns without Code Violations
Reset: 90_H
A_TSIMODE
TSI Detection Mode Register


76,*56<
1
Z
76,:&$
Z
Offset
04D_H

Data Sheet
233

&3+5$
Z
Reset Value
80_H


76,'(702'
Z
V4.0, 2010-02-19