TDA5240 Datasheet, PDF (257/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

ADC Input Selection Register
TDA5240
Appendix
Register Description
ADCINSEL
ADC Input Selection Register

8186('

Offset
08F_H

Field
Bits
UNUSED
7:3
ADCINSEL 2:0
RSSI Offset Register
Type
-
w
Description
UNUSED
Reset: 00_H
ADC Input Selection
000_B RSSI
001_B Temperature
010_B VDDD / 2
011_B n.u.
100_B n.u.
101_B n.u.
110_B n.u.
111_B n.u.
Reset: 0_H
Reset Value
00_H


$'&,16(/
Z
RSSIOFFS
RSSI Offset Register

Field
Bits
RSSIOFFS 7:0
RSSI Slope Register
Offset
090_H
566,2))6
Z
Type
w
Description
RSSI Offset Compensation Value
Min: 00h= -256
Max: FFh= 254
Reset: 80_H
Reset Value
80_H

Data Sheet
257
V4.0, 2010-02-19