TDA5240 Datasheet, PDF (145/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Reference
# _Parameter
Symbol Limit Values Unit
min. typ. max.
Test Conditions
Remarks
Timing SPI-Bus Characteristics
J1
Clock frequency
f_clock
2.2
MHz Note: A high SPI clock
rate during data reception
can reduce sensitivity
J2
Clock High time
t_{CLK_H}
200
J3
Clock Low time
t_{CLK_L}
200
J4
Active setup time
t_setup
200
J5
Not active setup time t_{not_setup}
200
J6
Active hold time
t_hold
200
J7
Not active hold time t_{not_hold}
200
J8
Deselect time
t_Deselect
200
J9
SDI setup time
t_{SDI_setup}
100
J10 SDI hold time
t_{SDI_hold}
100
J11 Clock low to SDO
valid
t_{CLK_SDO}
ns
ns
ns
ns
ns
ns
ns
ns
ns
145
ns
■
■
■
■
■
■
■
■
■
@ C_load = 80 pF
■
High Power Pad not
enabled (Normal Mode)
(see register PPCFG2
and CMC0)
J12 Clock low to SDO
valid
t_{CLK_SDO}
40
ns
@ C_load = 10 pF
High Power Pad not
enabled (Normal Mode)
(see register PPCFG2
and CMC0)
J13 SDO rise time
t_{SDO_r}
90
ns
@ C_load = 80 pF
■
J14 SDO fall time
t_{SDO_f}
90
ns
@ C_load = 80 pF
■
J15 SDO rise time
t_{SDO_r}
15
ns
@ C_load = 10 pF
■
J16 SDO fall time
t_{SDO_f}
15
ns
@ C_load = 10 pF
■
J17 SDO disable time
t_{SDO_disable}
25
ns
■
1) Please note that the system bandwidth is smaller than the smallest bandwidth in the signal path.
Data Sheet
145
V4.0, 2010-02-19