TDA5240 Datasheet, PDF (228/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
NDSEL
5:4
NDTL
3:2
NDPDSR
1:0
Type
w
w
w
Description
Signal and Noise Detector Selection
00_B Signal detection (=Squelch) only. This mode is recommended for
ASK.
01_B Noise detection only
10_B Signal and noise detection simultaneously
11_B Signal and noise detection simultaneously, but the FSK noise
detect signal is valid only if the SIGDETLO threshold is exceeded.
This is the recommended mode for FSK.
Reset: 0_H
FSK Noise Detector Threshold Level
00_B 1/2
01_B 3/8
10_B 1/4
11_B 1/8
Reset: 1_H
FSK Noise Detector - Peak Detector Slew Rate
00_B 1/256
01_B 1/128
10_B 1/64
11_B 1/32
Reset: 3_H
Clock and Data Recovery P Configuration Register
A_CDRP
Clock and Data Recovery P Configuration
Register
Offset
046_H


3'65
Z

3+'(1
Z

3+'(1
Z


39$/
Z
Reset Value
E6_H


36$7
Z
Field
PDSR
Bits
Type Description
7:6
w
Peak-Detector slew rate. The slew rate of the Peak-Detector in the
clock-recovery path will be set with
PDSR. Actually, Peak-Detector part of Signal Detector Block
00_B up/down = 1/64
01_B up = 1/64; down = 1/128
10_B up = 1/32; down = 1/128
11_B up = 1/32; down = 1/256
Reset: 3_H
Data Sheet
228
V4.0, 2010-02-19