TDA5240 Datasheet, PDF (25/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
2.4.5 Sigma-Delta Fractional-N PLL Block
The Sigma-Delta Fractional-N PLL is fully integrated on chip. The Voltage Controlled
Oscillator (VCO) with on-chip LC-tank runs at approximately 3.6 GHz and is first divided
with a band select divider by 1, 2 or 3 and then with an I/Q-divider by 4 which provides
an orthogonal local oscillator signal for the first image reject mixer with the necessary
high accuracy.
The multi-modulus divider determines the channel selection and is controlled by a
3^rd order Sigma-Delta Modulator (SDM). A type IV phase detector, a charge pump with
programmable current and an on-chip loop filter closes the phase locked loop.
To 1^st mixer
3.6 GHz VCO Loop Filter
CP
IQ Divider
÷4
Band Select
÷1/÷2/÷3
Channel FN
Multi-
modulus
Divider
ΣΔ Modulator
AFC filter
AFC-data
Figure 9 Synthesizer Block Diagram
PFD
QOSC
22MHz
Data Sheet
25
V4.0, 2010-02-19