TDA5240 Datasheet, PDF (270/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
FIFOLK
1
Type
w
XTALHPMS 0
w
Chip Mode Control Register 0
Description
Lock Data FIFO at EOM
0_B FIFO lock is disabled
1_B FIFO lock is enabled at EOM. This also locks the digital receive
chain at EOM until release from FIFO lock state.
Reset: 0_H
XTAL High Precision Mode in Sleep Mode
0_B Disabled
1_B Enabled
Reset: 0_H
CMC0
Chip Mode Control Register 0
Offset
0A6_H

6'2+33(
1
Z

,1,73//
+2/'
Z

+2/'
Z

&/.287(
1
Z


0&6
Z
Reset Value
10_H

6/5;(1
Z

06(/
Z
Field
Bits
SDOHPPEN 7
INITPLLHOLD 6
HOLD
5
CLKOUTEN 4
Type
w
w
w
w
Description
SDO High Power Pad Enable
0_B Normal
1_B High Power
Reset: 0_H
Init PLL after coming from HOLD (when new channel programmed).
This requires an additional Channel Hop Time before initialization of the
Digital Receiver.
0_B No init of PLL
1_B Init of PLL
Reset: 0_H
Holds the chip in the Register Configuration state (only in Run Mode
Slave)
0_B Normal Operation
1_B Jump into the Register Config state Hold
Reset: 0_H
CLK_OUT Enable
0_B Disabled
1_B Enable programmable clock output
Reset: 1_H
Data Sheet
270
V4.0, 2010-02-19