TDA5240 Datasheet, PDF (232/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
TOLCHIPL 2:0
Type
w
CDR DC Bit Tolerance Register
Description
Duty Cycle Tolerance for Chip Border Low Level. Represents the
number of 1/16 bit sample deviation from the ideal chip border
where an edge can occur in direction to the previous chip border.
Reset: 4_H
A_CDRTOLB
CDR DC Bit Tolerance Register



8186('

Offset
04A_H

72/%,7+
Z
Reset Value
1E_H


72/%,7/
Z
Field
Bits
UNUSED
7:6
TOLBITH
5:3
TOLBITL
2:0
Type
-
w
w
Description
UNUSED
Reset: 0_H
Duty Cycle Tolerance for Bit Border High Level. Represents the
number of 1/16 bit sample deviation from the ideal bit border where
an edge can occur in direction to the following bit border.
Reset: 3_H
Duty Cycle Tolerance for Bit Border Low Level. Represents the
number of 1/16 bit sample deviation from the ideal bit border where
an edge can occur in direction to the previous bit border.
Reset: 6_H
Timing Violation Window Register
A_TVWIN
Timing Violation Window Register

Offset
04B_H
79:,1
Z
Reset Value
28_H

Data Sheet
232
V4.0, 2010-02-19