TDA5240 Datasheet, PDF (60/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
The third criterion is the loss of symbol synchronization. Depending on the x_TVWIN
register, the Sync signal persists for a certain amount of time after the end of the pattern
has been reached. Therefore, more bits could be written into the FIFO than sent. The
three EOM criteria can be combined with each other. If one of the selected EOM criteria
is fulfilled, an EOM signal will be generated.
TSI Gap Mode
The TSI Gap Mode is only used if TSI patterns contain a gap that is not synchronous to
the data rate, e.g. if a gap is 7.7 data bits, or if a gap is longer than 10 data bits. In all
other cases, gaps should be included in the TSI pattern as code violations.
Because of its complexity in configuration, TSI Gap Mode should be only used in
applications as noted above!
For these special protocols, it is possible to lock the actual data frequency during a long
Code Violation period inside a TSI (x_TSIGAP must have a minimum of 8 chips).
TSIGAP is used to lock the PLL after TSI A was found. After the lock period, two different
resynchronization modes are available (TSI Gap ReSYNchronization, TSIGRSYN):
• Frequency readjustment (PLL starts from the beginning), TSIGRSYN = 1. In this
mode the T/2 gap resolution can be set in the 5 MSB x_TSIGAP register bits. The
value in GAPVAL (3 LSB in x_TSIGAP register) is not used. This is the preferred
mode in TSI Gap Mode.
valid data
RUNIN
TSI A
< 1bit
clock recovery reset
start point
all space or all mark
valid data
TSI GAP
PLL sync
GAPSync
TSI B
< 1bit
Figure 31
internal PLL sync
Clock Recovery Gap Resynchronization Mode TSIGRSYN = 1
• Phase readjustment only, TSIGRSYN = 0. In this mode, the value in GAPVAL is used
to correct the phase after the gap phase. Overall gap time can be defined in T/16
Data Sheet
60
V4.0, 2010-02-19