TDA5240 Datasheet, PDF (279/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description


63,$7
U
Field
SPIAT
Bits
Type
7:0
r
SPI Data Tracer Register
Description
SPI Address Tracer, Readout of the last address of a SFR Register
written by SPI
Reset: 00_H
SPIDT
SPI Data Tracer Register

Offset
0B4_H
63,'7
U
Reset Value
00_H

Field
Bits
SPIDT
7:0
SPI Checksum Register
Type
r
Description
SPI Data Tracer, Readout of the last written data to a SFR Register
by SPI
Reset: 00_H
SPICHKSUM
SPI Checksum Register

Offset
0B5_H
63,&+.680
UF
Field
Bits
SPICHKSUM 7:0
Type
rc
Description
SPI Checksum Readout
Reset: 00_H
Reset Value
00_H

Data Sheet
279
V4.0, 2010-02-19