TDA5240 Datasheet, PDF (24/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
The resulting CLK_OUT frequency can be calculated by:
Functional Description
f_CLKOUT = _2-----â‹---d---i--v----i--sf--^s_i--^y_o---^s-n---f---a---c---t--o---r
Enable
Enable
f_{s y s}
20 Bit Counter
2 x f_{CLK_OUT}
D ivid e
by 2
f_{C LK _OU T}
Figure 8 External Clock Generation Unit
The maximum CLK_OUT frequency is limited by the driver capability of the PPx pin and
depends on the external load connected to this pin. Please be aware that large loads
and/or high clock frequencies at this pin may interfere with the receiver and reduce
performance.
After Reset the PPx pin is activated and the division factor is initialized to 11 (equals
f_{CLK_OUT} = 998 kHz).
A clock output frequency higher than 1 MHz is not supported.
For high sensitivity applications, the use of the external clock generation unit is not
recommended.
Data Sheet
24
V4.0, 2010-02-19