TDA5240 Datasheet, PDF (56/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
of Bi-phase encoded data (chips). Basically the Framer consists of two identical
correlators of 16 chips in length. It allows a Telegram Start Identifier (TSI) to be
composed of Bi-phase encoded “Zeros” and “Ones”. The active length of each of the 16
chips correlators is defined independently in the x_TSILENA and x_TSILENB registers.
The pattern to match is defined as a sequence of chips in the x_TSIPTA0, x_TSIPTA1,
x_TSIPTB0 and x_TSIPTB1 registers.
Note that the RUNIN length shown in the figures below is the maximum needed RUNIN
with the length of 8 chips. Further details on the needed RUNIN time of the receiver can
be seen in Chapter 2.4.8.3 Clock and Data Recovery.
Bi-phase- /
Manchester -
Decoder
Data
Data Clock
Code-Violation ^CV
Detector
EOM-Detector
Data
Data Clock
EOMCV
EOMSYLO
EOMDATLEN
EOM
x_EOMDLEN
x_EOMDLENP
Sync
from CR ^{Chip-Data Clock}
from Chip-Data
Data -
Slicer
TSI wild card
x_TSIMODE(6:3)
MRB
Delay-Line 16-bit
Correlator A 16-bit
LRB
TSI Data-Pattern
TSI Data -Pattern
LSB
MSB LSB
MSB
Correlator A
Controller
x_TSILENA
Frame
Synchron -
ization
Controller
FSync
CorrAMatch
MUX
MRB
Delay-Line 16-bit
Correlator B 16-bit
LRB
TSI Data-Pattern
TSI Data -Pattern
LSB
MSB LSB
MSB
Correlator B
Controller
x_TSILENB
x_TSIMODE
x_TSIGAP
Figure 26 Frame Synchronization Unit
Data Sheet
56
V4.0, 2010-02-19