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| TDA5240 Datasheet, PDF (269/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver | |||
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TDA5240
Appendix
Register Description
Field
Bits
EXTEOM
0
Type
wc
Chip Mode Control Register 1
Description
Force EOM signal in external data processing mode
(*_CHCFG.EXTROC = 1H or 2H)
0B no external EOM signal forced
1B external EOM signal forced
Reset: 0H
CMC1
Chip Mode Control Register 1
Offset
0A5H
8186('
(201&)
*
Z
727,01
&+
Z
,1,7),)
2
Z
)6,1,7)
,)2
Z
Reset Value
04H
),)2/.
Z
;7$/+30
6
Z
Field
Bits
UNUSED
7:6
EOM2NCFG 5
TOTIM2NCH 4
INITFIFO
3
FSINITFIFO 2
Type
-
w
w
w
w
Description
UNUSED
Reset: 0H
Continue with next Configuration in Self Polling Mode after EOM
detected in Run Mode Self Polling
0B Continue with Configuration A in Self Polling Mode
1B Continue with next Configuration in Self Polling Mode
Reset: 0H
Continue with next RF channel in Self Polling Mode after TOTIM
detected in Run Mode Self Polling. In case of single RF channel
application this means "continue with next Configuration" instead
of "continue with next RF channel".
0B Continue with Configuration A in Self Polling Mode
1B Continue with next RF channel in Self Polling Mode
Reset: 0H
Initialization of FIFO at Cycle Start
This Initialization of the FIFO can be configured in both Run Mode Slave
and Self Polling Mode. In Run Mode Slave this happens at the beginning.
In Self Polling Mode the initialization is done after Wake up found
(switching from Self Polling Mode to Run Mode Self Polling).
0B Initialization disabled
1B Initialization enabled
Reset: 0H
Initialization of FIFO at Frame Start
0B Initialization disabled
1B Initialization enabled
Reset: 1H
Data Sheet
269
V4.0, 2010-02-19
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