TDA5240 Datasheet, PDF (253/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description




8186('
&/.287

Z
Field
Bits
UNUSED
7:4
CLKOUT2
3:0
RF Control Register
Type
-
w
Description
UNUSED
Reset: 0_H
Clock Out Divider: CLKOUT(19:0) = CLKOUT2(MSB) & CLKOUT1 &
CLKOUT0(LSB)
Min: 00002h = Clock divided by 2*2
Max: FFFFFh = Clock divided by ((2^20)-1)*2
Reg. value 00000h = Clock divided by (2^20)*2
Reset: 0_H
RFC
RF Control Register


8186('

Offset
089_H


5)2))
Z
,)$77
Z
Field
Bits
UNUSED
7:5
RFOFF
4
Type
-
w
Description
UNUSED
Reset: 0_H
Switch off RF-path (for RSSI trimming)
0_B RF path enabled
1_B RF path disabled
Reset: 0_H
Reset Value
07_H

Data Sheet
253
V4.0, 2010-02-19