TDA5240 Datasheet, PDF (67/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Functional Description
RUNIN
TSI
PAYLOAD
Figure 38 Structure of Payload Frame
Two important system parameters are described in this section: the Synchronization
Search Time Out (SYSRCTO) and the Inter-Frame Time. The processing sequence of
a payload frame is shown in Figure 39.
input data
RUNIN
TSI
RUNIN
CDR input
RUNIN
TSI
RUNIN
chip data available
PLL re-synchronization
data available
TSI
T₄
T₁
T₂
T₃
symbol sync found
Figure 39 Data Latency
RUNIN
T₂ T₂
The overall system latency time is calculated in two steps: T₁ is the delay between ADC
input (ASK) / limiter output (FSK) and the CDR input, and T₂ is the time between Symbol
Sync Found and the Framer output (decoded data available).
T₄ is the time between Symbol Sync Found and Chip Data output (RX mode TMCDS).
T₄ = 1 T. T is the nominal duration of one data bit.
T₁ latency time include: (T₁ = 12.5µs + 2 T)
• digital frontend processing delay
• matched filter computation time
• signal detector delay
T₂ latency time include: (T₂ = 1.5 T + 0.5 T¹⁾ )
• Data Slicer computation time
• Framer computation time.
1) The 0.5 T have to be added in case of activation of Bi-phase mark / space decoding mode and Data Slicer Bit
mode without Code Violation (see register x_SLCCFG)
Data Sheet
67
V4.0, 2010-02-19