TDA5240 Datasheet, PDF (276/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description


3/'/(1
U
Field
Bits
PLDLEN
7:0
Type
r
ADC Result High Byte Register
Description
Payload Data Length stored at TSI detection of the next message,
PLDLEN(9:0) = RFPLLACC.PLDLEN(MSB) & PLDLEN(LSB).
Cleared with INIT FIFO
Min. 000h = 0 bits received
Max. 3FFh = 1023 bits received
Reset: 00_H
ADCRESH
ADC Result High Byte Register

Offset
0AE_H
$'&5(6+
UF
Reset Value
00_H

Field
Bits
ADCRESH 7:0
Type
rc
ADC Result Low Byte Register
Description
ADC Result Value ADCRES(9:0) = ADCRESH(7:0) & ADCRESL(1:0)
Note: RC for control signal generation only, no clear
Reset: 00_H
ADCRESL
ADC Result Low Byte Register

8186('

Offset
0AF_H


$'&(2&
U
Reset Value
00_H


$'&5(6/
U
Data Sheet
276
V4.0, 2010-02-19