TDA5240 Datasheet, PDF (262/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
SPMIP
Bits
Type Description
7:0
w
Self Polling Mode Idle Periods value
Min: 01h = 1 (Master) Period
Max: FFh = 255 (Master) Periods
Reg. value 00h = 256 (Master) Periods
Reset: 01_H
Self Polling Mode Control Register
SPMC
Self Polling Mode Control Register

8186('

Offset
098_H


630$,(1
Z
Reset Value
00_H


6306(/
Z
Field
Bits
UNUSED
7:3
SPMAIEN
2
SPMSEL
1:0
Type
-
w
w
Description
UNUSED
Reset: 00_H
Self Polling Mode Active Idle Enable
0_B Disabled
1_B Enabled
Reset: 0_H
Self Polling Mode Selection
00_B Constant On/Off (COO)
01_B Fast Fall Back to Sleep (FFB)
10_B Mixed Mode (MM, Combination of Const On/Off and Fast Fall Back
to Sleep for different Configurations: COO, FFB, FFB, FFB)
11_B Permanent Wake Up Search (PWUS)
Reset: 0_H
Self Polling Mode Reference Timer Register
SPMRT
Self Polling Mode Reference Timer Register
Offset
099_H

63057
Z
Data Sheet
262
Reset Value
01_H

V4.0, 2010-02-19