TDA5240 Datasheet, PDF (213/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
AFCAGCD 7:0
Type
w
Description
AFC/AGC Freeze Delay Counter Division Ratio
The base period for the delay counter is the 8-16 samples/chip
(predecimation strobe) divided by 4
Reset: 00_H
AFC Start/Freeze Configuration Register
A_AFCSFCFG
AFC Start/Freeze Configuration Register
Offset
02C_H

8186('


$)&%/$6
.

$)&5(6$
7&&
Z
Z


$)&)5((=(
Z
Reset Value
00_H


$)&67$57
Z
Field
Bits
UNUSED
7
AFCBLASK 6
AFCRESATC 5
C
AFCFREEZE 4:2
Type
-
w
w
w
Description
UNUSED
Reset: 0_H
AFC blocking during a low phase in the ASK signal
0_B Disabled
1_B Enabled
Reset: 0_H
Enable AFC Restart at Channel Change and at the beginning of the
current configuration in Self Polling Mode
and at leaving the HOLD state (when bit CMC0.INITPLLHOLD is set) in
Run Mode Slave
0_B Disabled
1_B Enabled
Reset: 0_H
AFC Freeze Configuration
When selecting a Level criterion here,
please note to use the same Level criterion as for Wake-Up
000_B Stay ON
001_B Freeze on RSSI Event + Delay (AFCAGCDEL)
010_B Freeze on Signal Recognition Event + Delay (AFCAGCDEL)
011_B Freeze on Symbol Synchronization + Delay (AFCAGCDEL)
100_B SPI Command - write to EXTPCMD.AFCMANF bit
101_B n.u.
110_B n.u.
111_B n.u.
Reset: 0_H
Data Sheet
213
V4.0, 2010-02-19