TDA5240 Datasheet, PDF (235/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

TDA5240
Appendix
Register Description
Field
Bits
TSILENA
4:0
TSI Length Register B
Type
w
Description
TSI A Length (in chips):
(11_H up to 1F_H not used)
Min: 01 = 1 Chip; Be aware that such small values makes it
impossible to find the right phase of the pattern in the data stream and
therefore wrong data and code violations can be generated.
Max: 10h = 16 Chips = 8 Bit
Reset: 00_H
A_TSILENB
TSI Length Register B


8186('

Offset
04F_H

76,/(1%
Z
Field
Bits
UNUSED
7:5
TSILENB
4:0
Type
-
w
TSI Gap Length Register
Description
UNUSED
Reset: 0_H
TSI B Length (in chips):
(11_H up to 1F_H not used)
Min:
For 16 Bit TSI Mode:
Min: 00h = 0 Chip (see also A_TSILENA)
For all other TSI Modes:
Min: 01h = 1 Chip (see also A_TSILENA)
Max: 10h = 16 Chips = 8 Bit
Reset: 00_H
Reset Value
00_H

A_TSIGAP
TSI Gap Length Register

76,*$3
Z
Offset
050_H

Reset Value
00_H


*$39$/
Z
Data Sheet
235
V4.0, 2010-02-19