TDA5240 Datasheet, PDF (166/284 Pages) Infineon Technologies AG – Enhanced Sensitivity Multi-Channel Quad-Configuration Receiver

Appendix - Registers Chapter
Register Overview
TDA5240
Appendix
Register Overview
Table 1 Register Overview
Register Short Name Register Long Name
Offset Address
Appendix - Registers Chapter, Register Description
A_MID0
A_MID1
A_MID2
A_MID3
A_MID4
A_MID5
A_MID6
A_MID7
A_MID8
A_MID9
A_MID10
A_MID11
A_MID12
A_MID13
A_MID14
A_MID15
A_MID16
A_MID17
A_MID18
A_MID19
A_MIDC0
A_MIDC1
A_IF1
A_WUC
A_WUPAT0
A_WUPAT1
A_WUBCNT
A_WURSSITH1
A_WURSSIBL1
Message ID Register 0
Message ID Register 1
Message ID Register 2
Message ID Register 3
Message ID Register 4
Message ID Register 5
Message ID Register 6
Message ID Register 7
Message ID Register 8
Message ID Register 9
Message ID Register 10
Message ID Register 11
Message ID Register 12
Message ID Register 13
Message ID Register 14
Message ID Register 15
Message ID Register 16
Message ID Register 17
Message ID Register 18
Message ID Register 19
Message ID Control Register 0
Message ID Control Register 1
IF1 Register
Wake-Up Control Register
Wake-Up Pattern Register 0
Wake-Up Pattern Register 1
Wake-Up Bit or Chip Count Register
RSSI Wake-Up Threshold for Channel 1 Register
RSSI Wake-Up Blocking Level Low Channel 1
Register
000_H
001_H
002_H
003_H
004_H
005_H
006_H
007_H
008_H
009_H
00A_H
00B_H
00C_H
00D_H
00E_H
00F_H
010_H
011_H
012_H
013_H
014_H
015_H
016_H
017_H
018_H
019_H
01A_H
01B_H
01C_H
A_WURSSIBH1
RSSI Wake-Up Blocking Level High Channel 1
Register
01D_H
A_WURSSITH2
RSSI Wake-Up Threshold for Channel 2 Register 01E_H
Page Number
193
193
193
194
194
194
195
195
196
196
196
197
197
197
198
198
198
199
199
200
200
200
201
202
203
204
204
205
205
206
206
Data Sheet
166
V4.0, 2010-02-19