Z32F0641MCU Datasheet, PDF (99/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
16-Bit Timer
Tn.CR1 Timer n Control Register 1
The Timer Control Register 1 is a 16-bit register.
The timer module should be accurately configured prior to operating it. When a target purpose is defined, the
timer can be configured in the TnCR1 register.
T0.CR1=0x4000_3000, T1.CR1=0x4000_3020
T2.CR1=0x4000_3040, T3.CR1=0x4000_3060
T8.CR1=0x4000_3100, T9.CR1=0x4000_3120
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
000
RW RW RW RW
RW
RW
00
00
RW
RW
15 SSYNC
14 CSYNC
13 UAO
12 OUTPOL
8
ADCTRGEN
7
STARTLVL
6
CKSEL[2:0]
4
3
CLRMOD
2
1
MODE
0
Synchronize start counter with other synchronized timer
s
0
Single counter mode
1
Synchronized counter start mode
Synchronize clear counter with other synchronized timer
s
0
Single counter mode
1
Synchronized counter clear mode
Select GRA, GRB update mode
0
Writing GRA or GRB takes effect after current
period
1
Writing GRA or GRB takes effect in current peri
od
Timer output polarity
0
Normal output
1
Negated output
ADC Trigger enable control
0
Disable adc trigger
1
Enable adc trigger
Timer output polarity control
0
Default output level is HIGH
1
Defulat output level is LOW
Counter clock source select
000 PCLK/2
001 PCLK/4
010 PCLK/16
011 PCLK/64
10X MCCR3 clock setting
11X TnIO pin input (TnIO pin must be set as input
mode)
Clear select when capture mode
00 Rising edge clear mode
01 Falling edge clear mode
10 Both edge clear mode
11
None clear mode
Timer operation mode control
00 Normal periodic operation mode
01 PWM mode
10 One shot mode
11
Capture mode
PS034404-0417
PRELIMINARY
96