Z32F0641MCU Datasheet, PDF (40/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
PCER1 Peripheral Clock Enable Register 1
Prior to using a peripheral unit, its clock should be activated by writing 1 to the corresponding bit in the
PCER1/PCER2 register. The peripheral will not operate correctly until its clock is enabled.
To stop the clock of the peripheral unit, write 0 to the corresponding bit in the PCER1/PCER2 register.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
PCER1=0x4000_0030
8 765 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 1 1 1 1
25 TIMER9
24 TIMER8
19 TIMER3
18 TIMER2
17 TIMER1
16 TIMER0
11 GPIOD
10 GPIOC
9
GPIOB
8
GPIOA
4
DMA
3
2
1
0
TIMER9 clock enable
TIMER8 clock enable
TIMER3 clock enable
TIMER2 clock enable
TIMER1 clock enable
TIMER0 clock enable
GPIOD clock enable
GPIOC clock enable
GPIOB clock enable
GPIOA clock enable
DMA clock enable
Reserved
PS034404-0417
PRELIMINARY
37