Z32F0641MCU Datasheet, PDF (170/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Motor Pulse Width Modulator
Functional Description
The MPWM includes 3 channels, each of which controls a pair of outputs. In normal PWM mode, each
channel runs independently. Six PWM outputs can be generated.
Each PWM output is built with various settings. Figure 15.3 shows the diagram for generating PWM.
Figure 15.3. PWM Output Generation Chain
Normal PWM UP Count Mode Timing
In normal PWM mode, each channel runs independently. Six PWM outputs can be generated. An example of
the waveform is shown in Figure 15.4. Before PSTART is activated, the PWM output stays at the default value
L. When PSTART is enabled, the period counter starts up count up to the MP0.PRD count value. In the first
period, the MPWM does not generate a PWM pulse.
The PWM pulse is generated from the second period. The active level is derived at the start of the counter
value during duty value time.
PS034404-0417
PRELIMINARY
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