Z32F0641MCU Datasheet, PDF (103/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
16-Bit Timer
Tn.IER Timer Interrupt Enable Register
The Timer Interrupt Enable Register is an 8-bit register.
Each status flag of the timer block can issue the interrupt. To enable the interrupt, write 1 in the corresponding
bit in the TnIER register.
T0.IER=0x4000_301C, T1.IER=0x4000_303C
T2.IER=0x4000_305C, T3.IER=0x4000_307C
T8.IER=0x4000_311C, T9.IER=0x4000_313C
7
6
5
4
3
2
1
0
MAIE
MBIE
OVIE
0
0
0
0
0
0
0
0
W
RW
W
2
MAIE
1
MBIE
0
OVIE
GRA Match interrupt enable
0 Not effect
1 Enable match register A interrupt
GRB Match interrupt enable
0 Not effect
1 Enable match register B interrupt
Counter overflow interrupt enable
0 Not effect
1 Enable counter overflow interrupt
PS034404-0417
PRELIMINARY
100