Z32F0641MCU Datasheet, PDF (22/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
Figure 4.2 Clock Source Configuration
HCLK_FREE(4/8MHz)
Figure 4.3 System Clock Configuration
Each of the multiplexers for switching the clock source contains a circuit which allows glitch-free switching
between clock modes.
Clock name
MainOSC
PLL Clock
ROSC
Table 4.1 Clock Sources
Frequency
Description
XTAL(4MHz~8MHz)
External Crystal IOSC
8MHz ~ 80MHz
On Chip PLL
1MHz
Internal RING OSC
The PLL can synthesize the PLLCLK clock up to 80 MHz with the FIN reference clock. It also has an internal
pre-divider and post-divider.
PS034404-0417
PRELIMINARY
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