Z32F0641MCU Datasheet, PDF (66/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Port Control Unit
PCn.DER PORT n Debounce Enable Register
Every pin in the port has a digital debounce filter which can be configured by the PnDER registers. . The
Debounce clock can be configured in the DBCLKx registers.
15
14
13
12
11
10
9
8
7
PCA.DER=0x4000_100C, PCB.DER=0x4000_110C
PCC.DER=0x4000_120C, PCD.DER=0x4000_130C
6
5
4
3
2
1
0
PDEn
0000
RW
Pin debounce enable
0 Disable debounce filter
1 Enable debounce filter
PCn.IER PORT n Interrupt Enable Register
Each individual pin can be an external interrupt source. The edge trigger interrupt and level trigger interrupt
are both supported. The interrupt mode can be configured by setting the PnIER registers.
PCA.IER=0x4000_1010, PCB.IER=0x4000_1110
PCC.IER=0x4000_1210, PCD.IER=0x4000_1310
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PIE15 PIE14 PIE13 PIE12 PIE11 PIE10 PIE9 PIE8 PIE7 PIE6 PIE5 PIE4 PIE3 PIE2 PIE1 PIE0
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
PIEn
Pin interrupt enable
00 Interrupt disabled
01 Enable interrupt as level trigger mode
10 Reserved
11 Enable interrupt as edge trigger mode
PS034404-0417
PRELIMINARY
63