Z32F0641MCU Datasheet, PDF (142/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

0 START
Z32F0641 Product Specification
I2C Interface
1 Stop is enabled. When this bit is set, transmission will be stopped.
Transmission start bit in master mode.
0 Waits in slave mode.
1 Starts transmission in master mode.
Figure 14.2 INTDEL in Master Mode
ICn.SCLL I²C SCL LOW Duration Register
ICnSCLL is a 16-bit read/write register. SCL LOW time can be set by writing this register in Master Mode.
IC0.SDLL=0x4000_A018
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SCLL
0xFFFF
RW
15 SCLL
0
SCL LOW duration value.
SCLL = ( PCLK * SCLL[15:0] ) + 2*PCLKs
Default value is 0xFFFF.
Figure 14.3 SCL LOW Timing
PS034404-0417
PRELIMINARY
139