Z32F0641MCU Datasheet, PDF (195/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
12-Bit A/D Converter
Figure 16.5. ADC Trigger Timing in Burst Mode (SEQCNT = 3’b111, 8 Sequence Conversion )
ADC Sequential Conversion Mode Timing Diagram
To set sequential conversion mode, ADn.MR.AMOD is 2’b00 and ADn.MR.SEQCNT is not 2’b00.
The operation of sequential mode is almost the same as burst mode. The difference is the source of SOC.
Each SOC is made by the trigger of the SEQTRGx as each SEQCNT. See Figure 16.7.
Figure 16.6. ADC Sequential Mode Timing (When ADn.MR.AMOD = 0 and ADn.MR.SEQCNT ≠ 0)
PS034404-0417
PRELIMINARY
192