Z32F0641MCU Datasheet, PDF (91/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Direct Memory Access Controller
Figure 9.3. DMA Transfer from Peripheral to Memory
The timing diagram for a DMA transfer from memory to the peripheral is shown in Figure 9.4. 4-clock cycle
latency exists during accessing the peripheral. If the bus is occupied by a different bus master, there are
amount of bus waiting cycles.
Figure 9.4. DMA Transfer from Memory to Peripheral
The figure is an example N data transfers with the DMA. The DMA transfer is started when DCnSR.DMAEN is
set and will be cleared when all the number of transfer is completed.
Figure 9.5. N DMA Transfer Example
PS034404-0417
PRELIMINARY
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