Z32F0641MCU Datasheet, PDF (38/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
PER1 Peripheral Enable Register 1
Prior to using a peripheral unit, it requires to be activated by writing 1 to the corresponding bit in the
PER1/PER2 register. Until activation, the peripheral stays in Reset state.
To disable the peripheral unit, write 0 to the corresponding bit in the PER0/PER1 register, after which the
peripheral enters the Reset state.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8 765 4
PER1=0x4000_0028
3210
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000 0 1 1 1 1
25 TIMER9
24 TIMER8
19 TIMER3
18 TIMER2
17 TIMER1
16 TIMER0
11 GPIOD
10 GPIOC
9
GPIOB
8
GPIOA
4
DMA
3
2
1
0
TIMER9 function enable
TIMER8 function enable
TIMER3 function enable
TIMER2 function enable
TIMER1 function enable
TIMER0 function enable
GPIOD function enable
GPIOC function enable
GPIOB function enable
GPIOA function enable
DMA function enable
Reserved
PS034404-0417
PRELIMINARY
35