Z32F0641MCU Datasheet, PDF (194/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Functional Description
12-Bit A/D Converter
ADC Single Mode Timing
ADC conversion is started when ADCn.CR.ASTART is written as ‘1’ in single conversion mode. After
ADCnCR.ASTART is set, Start of Conversion (SOC) will be activated in 3 ADC clocks, ADCn.SR.EOCIRQ will
be set in 2 ADC clocks, and 2 PCLKs after the End of Conversion.
Figure 16.3. ADC Single Mode Timing ( when ADCn.MR.AMOD = ‘0’)
ADC Sequential Mode Timing Diagram
There are two sources to start conversion in burst mode: – TRG event (TIMER and MPWM) and ASTART.
When TRGSEL is set as the timer event trigger or MPWM event trigger, the conversion is started by the
trigger of ADn.TRG.BSTTRG (And.TRG[3:0]). For example, ADC conversion will be started by the trigger of
TIMER9 if ADn.TRG.BSTTRG is set as TIMER9. Once the BSTTRG’s trigger events occur, the ADC will
convert all channels defined in sequence (And.MR.SEQCNT contains the number of channels to convert).
See Figure 16.5.
Figure 16.4. ADC Burst Mode Timing (When ADCn.MR.AMOD = ‘1’)
PS034404-0417
PRELIMINARY
191