Z32F0641MCU Datasheet, PDF(141/205 Page) Zilog, Inc. – High Performance low-power Cortex-M3 core

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Z32F0641MCU Datasheet, PDF (141/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

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Z32F0641 Product Specification

ICn.SAR I2C Slave Address Register

ICn.SAR is an 8-bit read/write register. It shows the address in Slave Mode.

7

6

5

4

3

2

SVAD

0x00

RW

I2C Interface

IC0.SAR=0x4000_A00C

1

0

GCEN

0

RW

7 SVAD

1

0 GCEN

7-bit Slave Address

General call enable bit

0 General call is disabled.

1 General call is enabled.

ICn.CR I2C Control Register

ICn.CR is an 8-bits read/write register. The register can be set to configure I2C operation mode and

simultaneously allowed for I2C transactions to be kicked off.

IC0.CR=0x4000_A014

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

0

0

0

0

0

0

00

0

0

0

0

0

0

0

0

RW

R

RW RW RW

RW RW

9 INTDEL

8

7 IIF

5 SOFTRST

4 INTEN

3 ACKEN

1 STOP

Interval delay value between address and data transfer (or DATA and

DATA)

0 1 * ICnSCLL

1 2 * ICnSCLL

2 4 * ICnSCLL

3 8 * ICnSCLL

Interrupt status bit

0 Interrupt is inactive

1 Interrupt is active

Soft Reset enable bit.

0 Soft Reset is disabled.

1 Soft Reset is enabled..

Interrupt enabled bit.

0 Interrupt is disabled.

1 Interrupt is enabled.

ACK enable bit in Receiver mode.

0 ACK is not sent after receiving data.

1 ACK is sent after receiving data.

Stop enable bit. When this bit is set as â1â in transmitter mode, next

transmission will be stopped even though ACK signal has been received.

0 Stop is disabled.

PS034404-0417

PRELIMINARY

138

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