Z32F0641MCU Datasheet, PDF (69/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Functional Description
Port Control Unit
All the GPIO pins can be configured for different operations – inputs, outputs, and triggered interrupts (both
level and edge) through the PDU. The system is also able to disable ports by setting the PER1 and PCER1
registers in the SCU. By default, all pins are disabled (except for UART0/SPI0) so the developer must enable
these to operate.
All configuration parameters are protected by the Port Access Enable register. You must write the sequence
in order (0x15, 0x51) to the PORTEN register to configure any pin(s). Once the configuration is complete,
write any other value to the PORTEN register to lock it.
Note: Do not read in between the sequence; it will prevent the configuration registers from being unlocked.
When the input function of I/O port is used by the Pin Control Register, the output function of I/O port is
disabled. The Port function differs according to the Pin Mux Register.
The Input Data Register captures the data present on the I/O pin or debounced input data at every GPIO
Clock cycle.
INPUT CONTROL LOGIC
R/W
R/W
GPIO IN
00
FUNC 1 IN
01
FUNC 2 IN
10
FUNC 3 IN
11
De-Bounce
Enable Register
0
1
De-Bounce
Logic
VDD
P-MOS
200 Ohm 200 Ohm
R/W
Pin Mux
Register
AIN5V
GPIO OUT
00
FUNC 1 OUT
01
FUNC 2 OUT
10
FUNC 3 OUT
11
Pin
R/W
Control
Register
Control
Logic
VDD
P-MOS
N-MOS
VSS
OUTPUT CONTROL
LOGIC
Figure 5.4. Port Diagram
VDD
DIODE
DIODE
VSS
PAD
PS034404-0417
PRELIMINARY
66