Z32F0641MCU Datasheet, PDF (122/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
UART
Un.BFR Baud Rate Fraction Counter Register
The Baud Rate Fraction Counter Register is an 8-bit register.
7
6
5
4
3
U0.BFR=0x4000_8024, U1.BFR=0x4000_8124
2
1
0
BFR
0x00
RW
7
BFR
0
Fractions counter value.
0 Fraction counter is disabled
N Fraction counter enabled. Fraction compensation m
ode is operating. Fraction counter is incremented
by FCNT.
Baud Rate
1200
2400
4800
9600
19200
38400
57600
115200
Table 12.6 Example of Baud Rate Calculation
UART_PCLK=48 MHz
Divider
FCNT
Error (%)
1250
0
0.0%
625
0
0.0%
312
128
0.0%
156
64
0.0%
78
32
0.0%
39
16
0.0%
26
10
0.01%
13
5
0.01%
BFR = Float ∗ 256
The FCNT value can be calculated using the equation above. For example, if the target baud rate is 4800 bps
and UART_PCLK is 48 MHz, the BDR value is 312.5. Using the integer 312 as the BDR value and the floating
number 0.5, the FNCT value will be 128, as shown in the following calculation:
FCNT = 0.5 * 256 = 128
The 8-bit fractional counter will count up by the BFR value every (baud rate)/16 periods and whenever the
fractional counter overflows, the divisor value will increment by 1. Therefore, this period will be compensated.
In the next period, the divisor value will return to the original set value.
PS034404-0417
PRELIMINARY
119