English
Language : 

Z32F0641MCU Datasheet, PDF (165/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core
Z32F0641 Product Specification
Motor Pulse Width Modulator
MP0.IER[5:0] control bits are shared by duty match interrupt event and ADC trigger match interrupt event.
When ADC trigger mode is disabled, the interrupt is generated by the duty match condition. In other cases,
the interrupt is generated by the ADC trigger counter match condition. The ADC trigger mode is selected by
the ATMOD bit field in the ATRm register.
MP0.SR MPWM Status Register
The PWM Status Register is a 16-bit register.
MP0.SR=0x4000_4030
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
000
RW
RW
0
0
0
15 DOWN
14 IRQCNT
12
7
PRDIF
6
BOTIF
5
DWHIF
ATR6F
4
DVHIF
ATR5F
3
DUHIF
ATR4F
2
DWLIF
ATR3F
1
DVLIF
ATR2F
0
DULIF
ATR1F
0
0
0
0
0
0
0
0
0
RW RW RW RW RW RW RW RW
0 Current PWM Count mode is Up
1 Current PWM Count mode is Down
Interrupt count number of period match
(Interval PRDIRQ mode)
PWM Period Interrupt flag(write “1” to clear flag)
0 No interrupt occurred
1 Interrupt occurred
PWM Bottom Interrupt flag(write “1” to clear flag)
0 No interrupt occurred
1 Interrupt occurred
PWM duty WH interrupt flag(write “1” to clear flag)
(Duty interrupt is enabled if ATR6 was disabled)
0 No interrupt occurred
1 Interrupt occurred
PWM duty VH interrupt flag(write “1” to clear flag)
(Duty interrupt is enabled if ATR5 was disabled)
0 No interrupt occurred
1 Interrupt occurred
PWM duty UH interrupt flag(write “1” to clear flag)
(Duty interrupt is enabled if ATR4 was disabled)
0 No interrupt occurred
1 Interrupt occurred
PWM duty WL interrupt flag(write “1” to clear flag)
(Duty interrupt is enabled if ATR3 was disabled)
0 No interrupt occurred
1 Interrupt occurred
PWM duty VL interrupt flag(write “1” to clear flag)
(Duty interrupt is enabled if ATR2 was disabled)
0 No interrupt occurred
1 Interrupt occurred
PWM duty UL interrupt flag(write “1” to clear flag)
(Duty interrupt is enabled if ATR1 was disabled)
0 No interrupt occurred
1 Interrupt occurred
PS034404-0417
PRELIMINARY
162