Z32F0641MCU Datasheet, PDF (135/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
Serial Peripheral Interface
SS
SCK
MOSI
MISO
D7 D6 D5
D4 D3 _D2
D1
D0
D7
D6 D5
D4 D3 _D2
D1
D0
Figure 13.4 SPI Transfer Timing 2/4 (CPHA=0, CPOL=1, MSBF=1)
The timing of a SPI transfer where CPHA is one is shown in Figure 13.5 and Figure 13.6. Two wave forms are
shown for the SCLK signal -one for CPOL equals zero and another for CPOL equals one.
Similar to the previous cases, the falling edge of the nSS lines selects and activates the slave. Compared to
the previous cases, where CPHA equals zero, the transmission is not started and the MSB is not output by
the slave at this stage. The actual transfer is started by a software write to the SPnTDR of the master which
causes the clock signal to be generated. The first edge of the SCLK signal from its inactive to its active state
(rising edge if CPOL equals zero and falling edge if CPOL equals one) causes both the master and the slave
to output the MSB of the byte in the SPnTDR.
As shown in Figure 13.3 and Figure 13.4, there is no delay of half a SCLK-cycle. The SCLK line changes its
level immediately at the beginning of the first SCLK-cycle. The data on the input lines is read with the edge of
the SCLK line from its active to its inactive state (falling edge if CPOL equals zero and rising edge if CPOL
equals one). After eight clock pulses, the transmission is completed.
PS034404-0417
PRELIMINARY
132