Z32F0641MCU Datasheet, PDF (41/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
System Control Unit
PCER2 Peripheral Clock Enable Register 2
Prior to using a peripheral unit, its clock should be activated by writing 1 to the corresponding bit in the
PCER1/PCER2 register. The peripheral will not operate correctly until its clock is enabled.
To stop the clock of the peripheral unit, write 0 to the corresponding bit in the PCER1/PCER2 register.
PCER2=0x4000_0034
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00000000000000000000000100000001
21 ADC1
20 ADC0
16 MPWM0
9
UART1
8
UART0
4
I2C0
0
SPI0
ADC1 clock enable
ADC0 clock enable
MPWM0clock enable
UART1 clock enable
UART0 clock enable
I²C0 clock enable
SPI0 clock enable
PS034404-0417
PRELIMINARY
38