Z32F0641MCU Datasheet, PDF (128/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Pin Description
Z32F0641 Product Specification
Serial Peripheral Interface
Table 13.1 External Pins
Pin Name
SS0
SCK0
MOSI0
MISO0
Type
I/O
I/O
I/O
I/O
Description
SPI0 Slave select input / output
SPI0 Serial clock input / output
SPI0 Serial data ( Master output, Slave input )
SPI0 Serial data ( Master input, Slave output )
Registers
The base address of SPI is 0x4000_9000 and the register map is described in Table 13.3.
Table 13.2 SPI Base Address
Name
Base Address
SPI0
0x4000_9000
Name
SP0.TDR
SP0.RDR
SP0.CR
SP0.SR
SP0.BR
SP0.EN
SP0.LR
Offset
0x00
0x00
0x04
0x08
0x0C
0x10
0x14
Table 13.3 SPI Register Map
Type
Description
W
SPI0 Transmit Data Register
R
SPI0 Receive Data Register
RW
SPI0 Control Register
RW
SPI0 Status Register
RW
SPI0 Baud rate Register
RW
SPI0 Enable register
RW
SPI0 delay Length Register
Reset Value
-
0x000000
0x001020
0x000006
0x0000FF
0x000000
0x010101
SP0.TDR SPI Transmit Data Register
SP0.TDR is a 17-bit read/write register. It contains serial transmit data.
SP0.TDR=0x4000_9000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
000000000000000
TDR
0x00000
RW
16 TDR
0
Transmit Data Register
PS034404-0417
PRELIMINARY
125