Z32F0641MCU Datasheet, PDF (193/205 Pages) Zilog, Inc. – High Performance low-power Cortex-M3 core

Z32F0641 Product Specification
12-Bit A/D Converter
ADn.DDR ADCn DMA Data Register
The ADC DMA Data Register is a 16-bit register. This register is a temporary register only for DMA transfer
(A/D conversion data of just completed conversion).
15
14
13
12
11
10
9
8
7
ADC DMA Temporary Data
0x000
R
AD0.DDR=0x4000_B02C, AD1.DDR=0x4000_B12C
6
5
4
3
2
1
0
ADMACH
0x0
R
15 ADDMAR
4
3
ADMACH
0
ADC conversion result data (12-bit)
ADC data channel indicator
ADn.DR ADCn Sequence Data Register 0~7
ADC Data Registers are 16-bit registers holding the ADC conversion from the result register.
AD0.DR0=0x4000_B030, AD0.DR1=0x4000_B034, AD0.DR2=0x4000_B038, AD0.DR3=0x4000_B03C
AD0.DR4=0x4000_B040, AD0.DR5=0x4000_B044, AD0.DR6=0x4000_B048, AD0.DR7=0x4000_B04C
AD1.DR0=0x4000_B130, AD1.DR1=0x4000_B134, AD1.DR2=0x4000_B138, AD1.DR3=0x4000_B13C
AD1.DR4=0x4000_B140, AD1.DR5=0x4000_B144, AD1.DR6=0x4000_B148, AD1.DR7=0x4000_B14C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADCDATA
0x000
R
15 ADC DATA
4
ADC channel 0~7 data (12-bit)
PS034404-0417
PRELIMINARY
190